SH7046 Datasheet, PDF (137/611 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7046 Series

Section 7 User Break Controller (UBC)
7.2 Register Descriptions
The UBC has the following registers. For details on register addresses and register states during
each processing, refer to appendix A, Internal I/O Register.
• User break address register H (UBARH)
• User break address register L (UBARL)
• User break address mask register H (UBAMRH)
• User break address mask register L (UBAMRL)
• User break bus cycle register (UBBR)
• User break control register (UBCR)
7.2.1 User Break Address Register (UBAR)
The user break address register (UBAR) consists of two registers: user break address register H
(UBARH) and user break address register L (UBARL). Both are 16-bit readable/writable registers.
UBARH specifies the upper bits (bits 31 to 16) of the address for the break condition, while
UBARL specifies the lower bits (bits 15 to 0). The initial value of UBAR is H’00000000.
• UBARH Bits 15 to 0: specifies user break address 31 to 16 (UBA31 to UBA16)
• UBARL Bits 15 to 0: specifies user break address 15 to 0 (UBA15 to UBA0)
7.2.2 User Break Address Mask Register (UBAMR)
The user break address mask register (UBAMR) consists of two registers: user break address mask
register H (UBAMRH) and user break address mask register L (UBAMRL). Both are 16-bit
readable/writable registers. UBAMRH specifies whether to mask any of the break address bits set
in UBARH, and UBAMRL specifies whether to mask any of the break address bits set in UBARL.
• UBAMRH Bits 15 to 0: specifies user break address mask 31 to 16 (UBM31 to UBM16)
• UBAMRL Bits 15 to 0: specifies user break address mask 15 to 0 (UBM15 to UBM0)
Rev. 4.00 Dec 05, 2005 page 93 of 564
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