SH7046 Datasheet, PDF (191/611 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7046 Series

TIORL_0, TIORL_3, TIORL_4
Initial
Bit Bit Name value R/W
7
IOD3
0
R/W
6
IOD2
0
R/W
5
IOD1
0
R/W
4
IOD0
0
R/W
3
IOC3
0
R/W
2
IOC2
0
R/W
1
IOC1
0
R/W
0
IOC0
0
R/W
Section 10 Multi-Function Timer Pulse Unit (MTU)
Description
I/O Control D0 to D3
Specify the function of TGRD.
When TGRD is used as the buffer register of TGRB, this
setting is disabled, and input capture/output compare
does not occur.
See the following tables.
TIORL_0: Table 10.12
TIORL_3: Table 10.20
TIORL_4: Table 10.24
I/O Control C0 to C3
Specify the function of TGRC.
When TGRC is used as the buffer register of TGRA, this
setting is disabled, and input capture/output compare
does not occur.
See the following tables.
TIORL_0: Table 10.13
TIORL_3: Table 10.21
TIORL_4: Table 10.25
Rev. 4.00 Dec 05, 2005 page 147 of 564
REJ09B0270-0400