SH7046 Datasheet, PDF (164/611 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7046 Series

Section 8 Data Transfer Controller (DTC)
Table 8.3 Repeat Mode Register Functions
Register
DTMR
DTCRAH
DTCRAL
DTIAR
DTSAR
DTDAR
Values Written Back upon a Transfer Information Write
Function
When DTCRA is other than 1 When DTCRA is 1
Operation mode
control
DTMR
DTMR
Transfer count save DTCRAH
DTCRAH
Transfer count
DTCRAL – 1
DTCRAH
Initial address
(Not written back)
(Not written back)
Transfer source
address
Increment/decrement/fixed
(DTS = 0) Increment/
decrement/fixed
(DTS = 1) DTIAR
Transfer destination Increment/decrement/fixed
address
(DTS = 0) DTIAR
(DTS = 1) Increment/
decrement/fixed
DTSAR
or
DTDAR
Repeat area
Transfer
DTDAR
or
DTSAR
Figure 8.7 Memory Mapping in Repeat Mode
Block Transfer Mode: Performs the transfer of one block for each one activation. Either the
transfer source or transfer destination is designated as the block area.
The block length is specified between 1 and 65536. When the transfer of one block ends, the
initial state of the block size counter and the address register specified as the block area is restored.
The other address register is then incremented, decremented, or left fixed.
Rev. 4.00 Dec 05, 2005 page 120 of 564
REJ09B0270-0400