SH7046 Datasheet, PDF (157/611 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7046 Series

Section 8 Data Transfer Controller (DTC)
Initial
Bit Bit Name Value R/W Description
7
DTVEC7 0
R/W DTC Software Activation Vectors 7 to 0
6
DTVEC6 0
5
DTVEC5 0
4
DTVEC4 0
3
DTVEC3 0
2
DTVEC2 0
1
DTVEC1 0
R/W These bits specify the lower eight bits of the vector
R/W
addresses for DTC activation by software.
R/W
A vector address is calculated as H’0400 + DTVEC
(7:0). Always specify 0 for DTVEC0. For example, when
R/W
DTVEC7 to DTVEC0 = H’10, the vector address is
R/W H’0410. When the bit SWDTE is 0, these bits can be
R/W
written to.
0
DTVEC0 0
R/W
Notes: 1. For the NMIF and AE bits, only a 0 write after a 1 read is possible.
2. For the SWDTE bit, a 1 write is always possible, but a 0 write is possible only after a 1
is read.
8.2.9 DTC Information Base Register (DTBR)
The DTBR is a 16-bit readable/writable register that specifies the upper 16 bits of the memory
address containing DTC transfer information. Always access the DTBR in word or longword
units. If it is accessed in byte units the register contents will become undefined at the time of a
write, and undefined values will be read out upon reads. The initial value is undefined.
8.3 Operation
8.3.1 Activation Sources
The DTC operates when activated by an interrupt or by a write to DTCSR by software. An
interrupt request can be directed to the CPU or DTC, as designated by the corresponding DTER
bit. At the end of a data transfer (or the last consecutive transfer in the case of chain transfer), the
activation source interrupt flag or corresponding DTER bit is cleared. The activation source flag,
in the case of RXI_2, for example, is the RDRF flag of SCI2.
When a DTC is activated by an interrupt, existing CPU mask level and interrupt controller
priorities have no effect. If there is more than one activation source at the same time, the DTC
operates in accordance with the default priorities.
Figure 8.2 shows a block diagram of activation source control. For details see section 6, Interrupt
Controller (INTC).
Rev. 4.00 Dec 05, 2005 page 113 of 564
REJ09B0270-0400