SH7046 Datasheet, PDF (50/611 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7046 Series

Section 1 Overview
Type
Operating
mode
control
Symbol
MD3
MD2
MD1
MD0
FWP
System
control
RES
MRES
WDTOVF
Interrupts NMI
IRQ3
IRQ2
IRQ1
IRQ0
IRQOUT
Multi
function
timer-pulse
unit (MTU)
TCLKA
TCLKB
TCLKC
TCLKD
TIOC0A
TIOC0B
TIOC0C
TIOC0D
TIOC1A
TIOC1B
I/O
Input
Name
Set the mode
Function
Set the operating mode. Inputs at these
pins should not be changed during
operation.
Input
Input
Input
Output
Input
Input
Output
Input
Protection
Pin for the flash memory. This pin is only
against write used in the flash memory version. Writing
operation into or erasing of flash memory can be
Flash memory protected. This pin becomes the Vcc pin
for the mask ROM version.
Power on
reset
When this pin is driven low, the chip
becomes to power on reset state.
Manual reset When this pin is driven low, the chip
becomes to manual reset state.
Watchdog
timer overflow
Output signal for the watchdog timer
overflow. If this pin need to be pulled-
down, use the resistor larger than 1 MΩ to
pull the pin down.
Non-
maskable
interrupt
Non-maskable interrupt pin. If this pin is
not used, it should be fixed high.
Interrupt
request 3 to 0
These pins request a maskable interrupt.
One of the level input or edge input can be
selected. In case of the edge input, one of
the rising edge, falling edge, or both can
be selected.
Interrupt
Shows that an interrupt cause has
request output occurred.
External clock These pins input an external clock.
input for MTU
timer
Input/
Output
Input/
Output
MTU input
The TGRA_0 to TGRD_0 input capture
capture/output input/output compare output/PWM output
compare
pins.
(channel 0)
MTU input
The TGRA_1 to TGRB_1 input capture
capture/output input/output compare output/PWM output
compare
pins.
(channel 1)
Rev. 4.00 Dec 05, 2005 page 6 of 564
REJ09B0270-0400