SH7046 Datasheet, PDF (40/611 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7046 Series

Table 6.3 Interrupt Response Time ........................................................................................ 86
Section 8 Data Transfer Controller (DTC)
Table 8.1 Interrupt Sources, DTC Vector Addresses, and Corresponding DTEs................... 116
Table 8.2 Normal Mode Register Functions .......................................................................... 119
Table 8.3 Repeat Mode Register Functions............................................................................ 120
Table 8.4 Block Transfer Mode Register Functions............................................................... 121
Table 8.5 Execution State of DTC ......................................................................................... 124
Table 8.6 State Counts Needed for Execution State............................................................... 124
Section 9 Bus State Controller (BSC)
Table 9.1 Address Map .......................................................................................................... 130
Table 9.2 On-chip Peripheral I/O Register Access................................................................. 132
Section 10 Multi-Function Timer Pulse Unit (MTU)
Table 10.1 MTU Functions ...................................................................................................... 134
Table 10.2 MTU Pins ............................................................................................................... 137
Table 10.3 CCLR0 to CCLR2 (channels 0, 3, and 4)............................................................... 141
Table 10.4 CCLR0 to CCLR2 (channels 1 and 2).................................................................... 141
Table 10.5 TPSC0 to TPSC2 (channel 0)................................................................................. 142
Table 10.6 TPSC0 to TPSC2 (channel 1)................................................................................. 142
Table 10.7 TPSC0 to TPSC2 (channel 2)................................................................................. 143
Table 10.8 TPSC0 to TPSC2 (channels 3 and 4) ..................................................................... 143
Table 10.9 MD0 to MD3.......................................................................................................... 145
Table 10.10 TIORH_0 (channel 0)............................................................................................. 148
Table 10.11 TIORH_0 (channel 0)............................................................................................. 149
Table 10.12 TIORL_0 (channel 0) ............................................................................................. 150
Table 10.13 TIORL_0 (channel 0) ............................................................................................. 151
Table 10.14 TIOR_1 (channel 1) ............................................................................................... 152
Table 10.15 TIOR_1 (channel 1) ............................................................................................... 153
Table 10.16 TIOR_2 (channel 2) ............................................................................................... 154
Table 10.17 TIOR_2 (channel 2) ............................................................................................... 155
Table 10.18 TIORH_3 (channel 3)............................................................................................. 156
Table 10.19 TIORH_3 (channel 3)............................................................................................. 157
Table 10.20 TIORL_3 (channel 3) ............................................................................................. 158
Table 10.21 TIORL_3 (channel 3) ............................................................................................. 159
Table 10.22 TIORH_4 (channel 4)............................................................................................. 160
Table 10.23 TIORH_4 (channel 4)............................................................................................. 161
Table 10.24 TIORL_4 (channel 4) ............................................................................................. 162
Table 10.25 TIORL_4 (channel 4) ............................................................................................. 163
Table 10.26 Output Level Select Function................................................................................. 173
Rev. 4.00 Dec 05, 2005 page xl of xliv