SH7046 Datasheet, PDF (361/611 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7046 Series

Section 12 Serial Communication Interface (SCI)
Section 12 Serial Communication Interface (SCI)
This LSI has two independent serial communication interface (SCI) channels. The SCI can handle
both asynchronous and clocked synchronous serial communication. In asynchronous serial
communication mode, serial data communication can be carried out with standard asynchronous
communication chips such as a Universal Asynchronous Receiver/Transmitter (UART) or
Asynchronous Communication Interface Adapter (ACIA). A function is also provided for serial
communication between processors (multiprocessor communication function).
12.1 Features
• Choice of asynchronous or clocked synchronous serial communication mode
• Full-duplex communication capability
The transmitter and receiver are mutually independent, enabling transmission and reception to
be executed simultaneously.
Double-buffering is used in both the transmitter and the receiver, enabling continuous
transmission and continuous reception of serial data.
• On-chip baud rate generator allows any bit rate to be selected
External clock can be selected as a transfer clock source.
• Choice of LSB-first or MSB-first transfer (except in the case of asynchronous mode 7-bit data)
• Four interrupt sources
Four interrupt sources — transmit-end, transmit-data-empty, receive-data-full, and receive
error — that can issue requests.
The transmit-data-empty interrupt and receive data full interrupts can activate the data transfer
controller (DTC).
• Module standby mode can be set
Asynchronous mode
• Data length: 7 or 8 bits
• Stop bit length: 1 or 2 bits
• Parity: Even, odd, or none
• Multiprocessor bit: 1 or 0
• Receive error detection: Parity, overrun, and framing errors
• Break detection: Break can be detected by reading the RxD pin level directly in case of a
framing error
SCIS200C_000020020700
Rev. 4.00 Dec 05, 2005 page 317 of 564
REJ09B0270-0400