SH7046 Datasheet, PDF (475/611 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7046 Series

Section 15 Motor Management Timer (MMT)
Exiting High-Impedance State: The MMT output pins that have entered the high-impedance
state by the input level detection are released from this state by restoring them to their initial states
by means of a power-on reset, or by clearing all the POE flags in ICSR2 (POE4F to POE6F: bits
12 to 14).
15.8.5 Usage Note
1. To set the POE pin as a level-detective pin, a high level signal must be firstly input to the POE
pin.
2. To clear bits POE4F, POE5F, and POE6F to 0, read the ICSR2 register. Clear bits, which are
read as 1, to 0, and write 1 to the other bits in the register.
Rev. 4.00 Dec 05, 2005 page 431 of 564
REJ09B0270-0400