SH7046 Datasheet, PDF (338/611 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7046 Series

Section 10 Multi-Function Timer Pulse Unit (MTU)
The POE has input-level detection circuitry and output-level detection circuitry, as shown in the
block diagram of Figure 10.114.
TIOC3B
TIOC3D
TIOC4A
TIOC4C
TIOC4B
TIOC4D
Output level
detection circuit
Output level
detection circuit
Output level
detection circuit
OCSR
ICSR1
POE3
POE2
POE1
POE0
Input level detection circuit
Falling-edge
detection circuit
Low-level
detection circuit
High-
impedance
request control
signal
Interrupt request
(MTUPOE)
φ/8
φ/16
φ/128
Legend:
OCSR: Output level control/status register
ICSR1: Input level control/status register
Figure 10.114 POE Block Diagram
Rev. 4.00 Dec 05, 2005 page 294 of 564
REJ09B0270-0400