SH7046 Datasheet, PDF (101/611 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7046 Series

5.2 Resets
Section 5 Exception Processing
5.2.1 Types of Reset
Resets have the highest priority of any exception source. There are two types of resets: manual
resets and power-on resets. As table 5.5 shows, both types of resets initialize the internal status of
the CPU. In power-on resets, all registers of the on-chip peripheral modules are initialized; in
manual resets, they are not.
Table 5.5 Reset Status
Conditions for Transition
to Reset Status
Type
Power-on reset
Manual reset
RES
Low
High
High
WDT
Overflow

Overflow

MRES

High
Low
CPU/INTC
Initialized
Initialized
Initialized
Internal Status
On-Chip
Peripheral
Module
PFC, IO Port
Initialized
Initialized
Initialized
Not initialized
Not initialized Not initialized
5.2.2 Power-On Reset
Power-On Reset by RES Pin: When the RES pin is driven low, the LSI becomes to be a power-
on reset state. To reliably reset the LSI, the RES pin should be kept at low for at least the duration
of the oscillation settling time when applying power or when in standby mode (when the clock
circuit is halted) or at least 20 t_cyc when the clock circuit is running. During power-on reset, CPU
internal status and all registers of on-chip peripheral modules are initialized. See Appendix B, Pin
States, for the status of individual pins during the power-on reset status.
In the power-on reset status, power-on reset exception processing starts when the RES pin is first
driven low for a set period of time and then returned to high. The CPU will then operate as
follows:
1. The initial value (execution start address) of the program counter (PC) is fetched from the
exception processing vector table.
2. The initial value of the stack pointer (SP) is fetched from the exception processing vector table.
3. The vector base register (VBR) is cleared to H'00000000 and the interrupt mask bits (I3 to I0)
of the status register (SR) are set to H'F (B'1111).
Rev. 4.00 Dec 05, 2005 page 57 of 564
REJ09B0270-0400