SH7046 Datasheet, PDF (64/611 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7046 Series

Section 2 CPU
Addressing
Mode
PC relative
addressing
Instruction
Format
Effective Address Calculation
disp:8
The effective address is the sum of PC value and
the value that is obtained by doubling the sign-
extended 8-bit displacement (disp).
PC
disp
+
(sign-extended)
×
PC + disp × 2
Equation
PC + disp × 2
disp:12
2
The effective address is the sum of PC value and
the value that is obtained by doubling the sign-
extended 12-bit displacement (disp).
PC
disp
+
(sign-extended)
×
PC + disp × 2
PC + disp × 2
2
Rn
The effective address is the sum of the register PC PC + Rn
and Rn.
PC
+
PC + Rn
Immediate
addressing
#imm:8
#imm:8
#imm:8
Rn
The 8-bit immediate data (imm) for the TST, AND, 
OR, and XOR instructions is zero-extended.
The 8-bit immediate data (imm) for the MOV, ADD, 
and CMP/EQ instructions is sign-extended.
The 8-bit immediate data (imm) for the TRAPA

instruction is zero-extended and then quadrupled.
Rev. 4.00 Dec 05, 2005 page 20 of 564
REJ09B0270-0400