SH7046 Datasheet, PDF (62/611 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7046 Series

Section 2 CPU
Addressing
Mode
Instruction
Format
Effective Address Calculation
Pre-decrement @-Rn
indirect register
addressing
The effective address is the value obtained by
subtracting a constant from Rn. 1 is subtracted for
a byte operation, 2 for a word operation, and 4 for
a longword operation.
Rn
Rn – 1/2/4 _–
Rn – 1/2/4
1/2/4
Indirect register @(disp:4, The effective address is the sum of Rn and a 4-bit
addressing with Rn)
displacement (disp). The value of disp is zero-
displacement
extended, and remains unchanged for a byte
operation, is doubled for a word operation, and is
quadrupled for a longword operation.
Rn
disp
(zero-extended)
+
×
Rn + disp × 1/2/4
Equation
Byte:
Rn – 1 → Rn
Word:
Rn – 2 → Rn
Longword:
Rn – 4 → Rn
(Instruction is
executed with
Rn after this
calculation)
Byte:
Rn + disp
Word:
Rn + disp × 2
Longword:
Rn + disp × 4
Indirect
indexed
register
addressing
1/2/4
@(R0, Rn) The effective address is the sum of Rn and R0.
Rn
+
Rn + R0
Rn + R0
R0
Rev. 4.00 Dec 05, 2005 page 18 of 564
REJ09B0270-0400