SH7046 Datasheet, PDF (341/611 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7046 Series

Initial
Bit Bit Name value R/W
11 to 
9
All 0 R
8
PIE
0
R/W
7
POE3M1 0
R/W
6
POE3M0 0
R/W
5
POE2M1 0
R/W
4
POE2M0 0
R/W
3
POE1M1 0
R/W
2
POE1M0 0
R/W
Section 10 Multi-Function Timer Pulse Unit (MTU)
Description
Reserved
These bits are always read as 0. These bits should
always be written with 0
Port Interrupt Enable
This bit enables/disables interrupt requests when any of
the POE0F to POE3F bits of the ICSR1 are set to 1
0: Interrupt requests disabled
1: Interrupt requests enabled
POE3 mode 1, 0
These bits select the input mode of the POE3 pin
00: Accept request on falling edge of POE3 input
01: Accept request when POE3 input has been sampled
for 16 Pφ/8 clock pulses, and all are low level.
10: Accept request when POE3 input has been sampled
for 16 Pφ/16 clock pulses, and all are low level.
11: Accept request when POE3 input has been sampled
for 16 Pφ/128 clock pulses, and all are low level.
POE2 mode 1, 0
These bits select the input mode of the POE2 pin
00: Accept request on falling edge of POE2 input
01: Accept request when POE2 input has been sampled
for 16 Pφ/8 clock pulses, and all are low level.
10: Accept request when POE2 input has been sampled
for 16 Pφ/16 clock pulses, and all are low level.
11: Accept request when POE2 input has been sampled
for 16 Pφ/128 clock pulses, and all are low level.
POE1 mode 1, 0
These bits select the input mode of the POE1 pin
00: Accept request on falling edge of POE1 input
01: Accept request when POE1 input has been sampled
for 16 Pφ/8 clock pulses, and all are low level.
10: Accept request when POE1 input has been sampled
for 16 Pφ/16 clock pulses, and all are low level.
11: Accept request when POE1 input has been sampled
for 16 Pφ/128 clock pulses, and all are low level.
Rev. 4.00 Dec 05, 2005 page 297 of 564
REJ09B0270-0400