SH7046 Datasheet, PDF (13/611 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7046 Series

Item
12.6.1 Clock
Page
357
12.6.2 SCI
358
initialization (Clocked
Synchronous mode)
Figure 12.15 Sample
SCI Initialization
Flowchart
13.3.2 A/D
373
Control/Status
Registers 0 to 2
(ADCSR_0 to
ADCSR_2)
13.3.3 A/D Control 375
Registers_0 to 2
(ADCR_0 to ADCR_2)
14.2.2 Compare
389
Match Timer
Control/Status
Register_0 and
1(CMCSR_0,
CMCSR_1)
Revision (See Manual for Details)
Description amended
Eight serial clock pulses are output in the transfer of one
character, and when no transfer is performed, the clock is fixed
high. Only in reception, the serial clock is continued generating
until an overrun error is occurred or the RE bit is cleared to 0.
To execute reception in one-character units, select an external
clock as a clock source.
Figure amended
Set PFC of the external pin used
SCK, TxD, RxD
[4]
Set RIE, TIE, and TEIE bits
Set TE and RE bits in SCR to 1 ^[5]
<Transfer start>
Table amended
Initial
Bit
Bit Name Value
7
ADF
0
5
ADM1
0
4
ADM0
0
R/W
R/(W)^*
R/W
R/W
Description
[Clearing conditions]
• When 0 is written after reading ADF = 1
• When the DTC is activated by an ADI interrupt and
ADDR is read with the DISEL bit in DTMR of DTC = 0
10: Setting prohibited
11: Setting prohibited
When changing the operating mode, first clear the ADST
bit in the A/D control registers (ADCRs) to 0.
Table amended
Initial
Bit Bit Name Value R/W
4
ADST
0
R/W
Description
... In continuous scan mode, A/D conversion is
continuously performed for the selected channels in
sequence until this bit is cleared by a software, reset, or
in software standby mode or module standby mode.
Table amended
Initial
Bit Bit Name Value
7
CMF
0
R/W
R/(W)^*
Description
Compare Match Flag
This flag indicates whether or not the CMCNT and
CMCOR values have matched.
0: CMCNT and CMCOR values have not matched
1: CMCNT and CMCOR values have matched
[Clearing conditions]
• Write 0 to CMF after reading 1 from it
• When the DTC is activated by an CMI interrupt and
data is transferred with the DISEL bit in DTMR of
DTC = 0
Rev. 4.00 Dec 05, 2005 page xiii of xliv