SH7046 Datasheet, PDF (357/611 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7046 Series

Section 11 Watchdog Timer
11.5 Interrupts
During interval timer mode operation, an overflow generates an interval timer interrupt (ITI). The
interval timer interrupt is requested whenever the OVF flag is set to 1 in TCSR. OVF must be
cleared to 0 in the interrupt handling routine.
Table 11.2 WDT Interrupt Source (in Interval Timer Mode)
Name
ITI
Interrupt Source
TCNT overflow
Interrupt Flag
OVF
DTC Activation
Impossible
11.6 Usage Notes
11.6.1 Notes on Register Access
The watchdog timer’s TCNT, TCSR, and RSTCSR registers differ from other registers in being
more difficult to write to. The procedures for writing to and reading these registers are given
below.
Writing to TCNT and TCSR: These registers must be written by a word transfer instruction.
They cannot be written by byte transfer instructions.
TCNT and TCSR both have the same write address. The write data must be contained in the lower
byte of the written word. The upper byte must be H'5A (for TCNT) or H'A5 (for TCSR) (figure
11.6). This transfers the write data from the lower byte to TCNT or TCSR.
• Writing to TCNT
15
Address: H'FFFF8610
H'5A
87
0
Write data
• Writing to TCSR
15
Address: H'FFFF8610
H'A5
87
0
Write data
Figure 11.6 Writing to TCNT and TCSR
Rev. 4.00 Dec 05, 2005 page 313 of 564
REJ09B0270-0400