SH7046 Datasheet, PDF (391/611 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7046 Series

Section 12 Serial Communication Interface (SCI)
12.4.6 Serial data reception (Asynchronous mode)
Figure 12.8 shows an example of the operation for reception in asynchronous mode. In serial
reception, the SCI operates as described below.
1. The SCI monitors the communication line, and if a start bit is detected, performs internal
synchronization, receives receive data in RSR, and checks the parity bit and stop bit.
2. If an overrun error (when reception of the next data is completed while the RDRF flag is still
set to 1) occurs, the OER bit in SSR is set to 1. If the RIE bit in SCR is set to 1 at this time, an
ERI interrupt request is generated. Receive data is not transferred to RDR. The RDRF flag
remains to be set to 1.
3. If a parity error is detected, the PER bit in SSR is set to 1 and receive data is transferred to
RDR. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt request is generated.
4. If a framing error (when the stop bit is 0) is detected, the FER bit in SSR is set to 1 and receive
data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt
request is generated.
5. If reception finishes successfully, the RDRF bit in SSR is set to 1, and receive data is
transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an RXI interrupt request is
generated. Because the RXI interrupt processing routine reads the receive data transferred to
RDR before reception of the next receive data has finished, continuous reception can be
enabled.
Start
1 bit
Data
Parity Stop Start
bit bit bit
Data
Parity Stop
bit bit 1
RxD
0 D0 D1
D7 0/1 1 0 D0 D1
D7 0/1 1 ^{Idle state}
(mark state)
RDRF
FER
1 frame
RXI interrupt
request
generated
RDR data read and
RDRF flag cleared
to 0 in RXI interrupt
processing routine
ERI interrupt
request generated
by framing error
Figure 12.8 Example of SCI Operation in Reception (Example with 8-Bit Data,
Parity, One Stop Bit)
Rev. 4.00 Dec 05, 2005 page 347 of 564
REJ09B0270-0400