SH7046 Datasheet, PDF (397/611 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7046 Series

Section 12 Serial Communication Interface (SCI)
Initialization
[1]
Start transmission
Read TDRE flag in SSR
[2]
No
TDRE = 1
Yes
Write transmit data to TDR and
set MPBT bit in SSR
Clear TDRE flag to 0
All data transmitted?
Yes
Read TEND flag in SSR
TEND = 1
Yes
Break output?
Yes
Clear DR to 0
No
[3]
No
No
[4]
[1] SCI initialization:
Set the TxD pin using the PFC.
After the TE bit is set to 1, 1 is
output for one frame, and
transmission is enabled.
However, data is not transmitted.
[2] SCI status check and transmit
data write:
Read SSR and check that the
TDRE flag is set to 1, then write
transmit data to TDR. Set the
MPBT bit in SSR to 0 or 1.
Finally, clear the TDRE flag to 0.
[3] Serial transmission continuation
procedure:
To continue serial transmission,
be sure to read 1 from the TDRE
flag to confirm that writing is
possible, then write data to TDR,
and then clear the TDRE flag to
0. Checking and clearing of the
TDRE flag is automatic when the
DTC is activated by a transmit
data empty interrupt (TXI)
request, and data is written to
TDR.
[4] Break output at the end of serial
transmission:
To output a break in serial
transmission, first clear the port
data register (DR) to 0, then
clear the TE bit to 0 in SCR and
use the PFC to select the TxD
pin as an output port.
Clear TE bit in SCR to 0;
select the TxD pin
as an output port with the PFC
<End>
Figure 12.11 Sample Multiprocessor Serial Transmission Flowchart
Rev. 4.00 Dec 05, 2005 page 353 of 564
REJ09B0270-0400