SH7046 Datasheet, PDF (20/611 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7046 Series

4.1.1 Connecting a Crystal Resonator........................................................................... 47
4.1.2 External Clock Input Method............................................................................... 48
4.2 Function for Detecting the Oscillator Halt........................................................................ 49
4.3 Usage Notes ...................................................................................................................... 49
4.3.1 Note on Crystal Resonator ................................................................................... 49
4.3.2 Notes on Board Design ........................................................................................ 50
Section 5 Exception Processing....................................................................................... 53
5.1 Overview........................................................................................................................... 53
5.1.1 Types of Exception Processing and Priority ........................................................ 53
5.1.2 Exception Processing Operations......................................................................... 54
5.1.3 Exception Processing Vector Table ..................................................................... 55
5.2 Resets ................................................................................................................................ 57
5.2.1 Types of Reset ..................................................................................................... 57
5.2.2 Power-On Reset ................................................................................................... 57
5.2.3 Manual Reset ....................................................................................................... 58
5.3 Address Errors .................................................................................................................. 59
5.3.1 The Cause of Address Error Exception................................................................ 59
5.3.2 Address Error Exception Processing.................................................................... 60
5.4 Interrupts ........................................................................................................................... 60
5.4.1 Interrupt Sources.................................................................................................. 60
5.4.2 Interrupt Priority Level ........................................................................................ 61
5.4.3 Interrupt Exception Processing ............................................................................ 61
5.5 Exceptions Triggered by Instructions ............................................................................... 62
5.5.1 Types of Exceptions Triggered by Instructions ................................................... 62
5.5.2 Trap Instructions .................................................................................................. 62
5.5.3 Illegal Slot Instructions ........................................................................................ 63
5.5.4 General Illegal Instructions.................................................................................. 63
5.6 Cases when Exception Sources Are Not Accepted ........................................................... 64
5.6.1 Immediately after a Delayed Branch Instruction ................................................. 64
5.6.2 Immediately after an Interrupt-Disabled Instruction............................................ 64
5.7 Stack Status after Exception Processing Ends .................................................................. 65
5.8 Usage Notes ...................................................................................................................... 66
5.8.1 Value of Stack Pointer (SP) ................................................................................. 66
5.8.2 Value of Vector Base Register (VBR) ................................................................. 66
5.8.3 Address Errors Caused by Stacking of Address Error Exception Processing ...... 66
Section 6 Interrupt Controller (INTC)........................................................................... 67
6.1 Features ............................................................................................................................. 67
6.2 Input/Output Pins .............................................................................................................. 69
6.3 Register Descriptions ........................................................................................................ 69
Rev. 4.00 Dec 05, 2005 page xx of xliv