SH7046 Datasheet, PDF (438/611 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7046 Series

Section 14 Compare Match Timer (CMT)
14.5.2 Contention between CMCNT Word Write and Incrementation
If an increment occurs during the T2 state of the CMCNT counter word write cycle, the counter
write has priority, so no increment occurs. Figure 14.7 shows the timing.
CMCNT write cycle
T1 T2
Pφ
Address
CMCNT
Internal write
signal
CMCNT
input clock
CMCNT
N
M
CMCNT write data
Figure 14.7 CMCNT Word Write and Increment Contention
Rev. 4.00 Dec 05, 2005 page 394 of 564
REJ09B0270-0400