SH7046 Datasheet, PDF (117/611 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7046 Series

Section 6 Interrupt Controller (INTC)
6.3.3 IRQ Status Register (ISR)
ISR is a 16-bit register that indicates the interrupt request status of the external interrupt input pins
IRQ0 to IRQ3. When IRQ interrupts are set to edge detection, held interrupt requests can be
withdrawn by writing 0 to IRQnF after reading IRQnF = 1.
Initial
Bit Bit Name Value R/W
15 to 
8
All 0 R
7
IRQ0F
0
R/W
6
IRQ1F
0
R/W
5
IRQ2F
0
R/W
4
IRQ3F
0
R/W
3 to 0 
All 0 R/W
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
IRQ0 to IRQ3 Flags
These bits display the IRQ0 to IRQ3 interrupt request
status.
[Setting condition]
• When interrupt source that is selected by ICR1 and
ICR2 has occurred.
[Clearing conditions]
• When 0 is written after reading IRQnF = 1
• When interrupt exception processing has been
executed at high level of IRQn input under the low
level detection mode.
• When IRQn interrupt exception processing has been
executed under the edge detection mode of falling
edge, rising edge or both of falling and rising edge.
• When the DISEL bit of DTMR of DTC is 0, after DTC
has been started by IRQn interrupt.
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 4.00 Dec 05, 2005 page 73 of 564
REJ09B0270-0400