SH7046 Datasheet, PDF (105/611 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7046 Series

Section 5 Exception Processing
Each interrupt source is allocated a different vector number and vector table offset. See section 6,
Interrupt Controller (INTC), and table 6.2, Interrupt Exception Sources, Vector Addresses and
Priorities, for more information on vector numbers and vector table address offsets.
5.4.2 Interrupt Priority Level
The interrupt priority is predetermined. When multiple interrupts occur simultaneously
(overlapped interruptions), the interrupt controller (INTC) determines their relative priorities and
starts the exception processing according to the results.
The priority of interrupts is expressed as priority levels 0 to 16, with priority 0 the lowest and
priority 16 the highest. The NMI interrupt has priority 16 and cannot be masked, so it is always
accepted. The priority level of the user break interrupt is 15. IRQ interrupt and on-chip peripheral
module interrupt priority levels can be set freely using the INTC’s interrupt priority registers A, D
to K (IPRA, IPRD to IPRK) as shown in table 5.8. The priority levels that can be set are 0 to 15.
Level 16 cannot be set. See section 6.3.4, Interrupt Priority Registers A, D to K (IPRA, IPRD to
IPRK), for more information on IPRA to IPRK.
Table 5.8 Interrupt Priority
Type
NMI
User break
IRQ
On-chip peripheral module
Priority Level
16
15
0–15
Comment
Fixed priority level. Cannot be masked.
Fixed priority level.
Set with interrupt priority registers A through K
(IPRA–IPRK).
5.4.3 Interrupt Exception Processing
When an interrupt occurs, the interrupt controller (INTC) ascertains its priority level. NMI is
always accepted, but other interrupts are only accepted if they have a priority level higher than the
priority level set in the interrupt mask bits (I3 to I0) of the status register (SR).
When an interrupt is accepted, exception processing begins. In interrupt exception processing, the
CPU saves SR and the program counter (PC) to the stack. The priority level value of the accepted
interrupt is written to SR bits I3 to I0. For NMI, however, the priority level is 16, but the value set
in I3 to I0 is H'F (level 15). Next, the start address of the exception service routine is fetched from
the exception processing vector table for the accepted interrupt, that address is jumped to and
execution begins. See section 6.6, Interrupt Operation, for more information on the interrupt
exception processing.
Rev. 4.00 Dec 05, 2005 page 61 of 564
REJ09B0270-0400