SH7046 Datasheet, PDF (548/611 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7046 Series

Section 21 Power-Down Modes
Oscillator
CK
NMI input
NMIE bit
SSBY bit
LSI state ^Program
NMI
exception
Exception
execution state _handling service routine
Software
standby mode
Oscillation WDT NMI exception
start time setting time handling
Oscillation stabilization
time
Figure 21.2 NMI Timing in Software Standby Mode
21.3.3 Module Standby Mode
Module standby mode can be set for individual on-chip peripheral functions.
When the corresponding MSTP bit in MSTCR is set to 1, module operation stops at the end of the
bus cycle and a transition is made to module standby mode. The CPU continues operating
independently.
When the corresponding MSTP bit is cleared to 0, module standby mode is cleared and the
module starts operating at the end of the bus cycle. In module standby mode, the internal states of
modules are initialized.
After reset clearing, the SCI, MTU, MMT, CMT, and A/D converter are in module standby mode.
When an on-chip supporting module is in module standby mode, read/write access to its registers
is disabled.
Rev. 4.00 Dec 05, 2005 page 504 of 564
REJ09B0270-0400