SH7046 Datasheet, PDF (151/611 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7046 Series

Section 8 Data Transfer Controller (DTC)
8.2 Register Descriptions
DTC has the following registers.
• DTC mode register (DTMR)
• DTC source address register (DTSAR)
• DTC destination address register (DTDAR)
• DTC initial address register (DTIAR)
• DTC transfer count register A (DTCRA)
• DTC transfer count register B (DTCRB)
These six registers cannot be directly accessed from the CPU.
When activated, the DTC transfer desired set of register information that is stored in an on-chip
RAM to the corresponding DTC registers. After the data transfer, it writes a set of updated register
information back to the RAM.
• DTC enable register A (DTEA)
• DTC enable register B (DTEB)
• DTC enable register C (DTEC)
• DTC enable register D (DTED)
• DTC enable register E (DTEE)
• DTC enable register F (DTEF)
• DTC control/status register (DTCSR)
• DTC information base register (DTBR)
For details on register addresses and register states during each processing, refer to appendix A,
Internal I/O Register.
Rev. 4.00 Dec 05, 2005 page 107 of 564
REJ09B0270-0400