SH7046 Datasheet, PDF (126/611 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7046 Series

Section 6 Interrupt Controller (INTC)
Interrupt
Source
MMT
A/D2

I/O (MMT)

Name
TGIM
TGIN
ADI2
Reserved by system
MMTPOE
Reserved by system
Vector Vector Table
No.
Starting Address IPR
Default
Priority
180
H'000002D0
IPRI3–IPRI0
High
181
H'000002D4
184
H'000002E0
188–196 H'000002F0–
H'00000310
IPRJ15–IPRJ12

200
H'00000320
204–212 H'00000330–
H'000003DC
IPRK15–IPRK12
Low
6.6 Interrupt Operation
6.6.1 Interrupt Sequence
The sequence of interrupt operations is explained below. Figure 6.3 is a flowchart of the
operations.
1. The interrupt request sources send interrupt request signals to the interrupt controller.
2. The interrupt controller selects the highest priority interrupt in the interrupt requests sent,
according to the priority levels set in interrupt priority level setting registers A–K (IPRA–
IPRK). Interrupts that have lower-priority than that of the selected interrupt are ignored.* If
interrupts that have the same priority level or interrupts within a same module occur
simultaneously, the interrupt with the highest priority is selected according to the default
priority order indicated in table 6.2.
3. The interrupt controller compares the priority level of the selected interrupt request with the
interrupt mask bits (I3–I0) in the CPU’s status register (SR). If the request priority level is
equal to or less than the level set in I3–I0, the request is ignored. If the request priority level is
higher than the level in bits I3–I0, the interrupt controller accepts the interrupt and sends an
interrupt request signal to the CPU.
4. When the interrupt controller accepts an interrupt, a low level is output from the IRQOUT pin.
5. The CPU detects the interrupt request sent from the interrupt controller when CPU decodes the
instruction to be executed. Instead of executing the decoded instruction, the CPU starts
interrupt exception processing (figure 6.5).
6. SR and PC are saved onto the stack.
7. The priority level of the accepted interrupt is copied to the interrupt mask level bits (I3–I0) in
the status register (SR).
Rev. 4.00 Dec 05, 2005 page 82 of 564
REJ09B0270-0400