SH7046 Datasheet, PDF (80/611 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7046 Series

Section 2 CPU
Instruction
Instruction Code
Operation
Execution
States T Bit
STS.L PR,@–Rn 0100nnnn00100010 Rn – 4 → Rn, PR → (Rn)
1

TRAPA #imm
11000011iiiiiiii PC/SR → stack area, (imm × 8

4 + VBR) → PC
Note: * The number of execution states before the chip enters sleep mode:
The execution states shown in the table are minimums. The actual number of states
may be increased when (1) contention occurs between instruction fetches and data
access, or (2) when the destination register of the load instruction (memory → register)
equals to the register used by the next instruction.
Rev. 4.00 Dec 05, 2005 page 36 of 564
REJ09B0270-0400