SH7046 Datasheet, PDF (176/611 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7046 Series

Section 9 Bus State Controller (BSC)
9.5 Bus Arbitration
This LSI has a bus arbitration function that, when a bus release request is received from a bus
masters, releases the bus to that module. There are two internal bus masters, the CPU and DTC.
The priority for arbitrate the bus mastership between these bus masters is:
DTC > CPU
9.6 On-chip Peripheral I/O Register Access
On-chip peripheral I/O registers are accessed from the bus state controller, as shown in Table 9.2.
Table 9.2 On-chip Peripheral I/O Register Access
On-chip
Peripheral
Module
MTU,
PFC,
SCI POE INTC PORT CMT A/D UBC WDT DTC MMT
Connected
bus width
Access cycle
8bit 16bit 16bit 16bit 16bit 16bit 16bit 16bit 16bit 16bit
2cyc^*1 2cyc^*1 2cyc^*2 2cyc^*1 2cyc^*1 2cyc^*1 3cyc^*2 3cyc^*2 3cyc^*2 2cyc^*1
Notes: 1. Converted to the peripheral clock.
2. Converted to the system clock.
Rev. 4.00 Dec 05, 2005 page 132 of 564
REJ09B0270-0400