SH7046 Datasheet, PDF(53/611 Page) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7046 Series

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SH7046 Datasheet, PDF (53/611 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7046 Series

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Section 2 CPU

Section 2 CPU

2.1 Features

â¢ General-register architecture

ï£§ Sixteen 32-bit general registers

â¢ Sixty-two basic instructions

â¢ Eleven addressing modes

ï£§ Register direct [Rn]

ï£§ Register indirect [@Rn]

ï£§ Register indirect with post-increment [@Rn+]

ï£§ Register indirect with pre-decrement [@-Rn]

ï£§ Register indirect with displacement [@disp:4,Rn]

ï£§ Register indirect with index [@R0, Rn]

ï£§ GBR indirect with displacement [@disp:8,GBR]

ï£§ GBR indirect with index [@R0,GBR]

ï£§ Program-counter relative with displacement [@disp:8,PC]

ï£§ Program-counter relative [disp:8/disp:12/Rn]

ï£§ Immediate [#imm:8]

2.2 Register Configuration

The register set consists of sixteen 32-bit general registers, three 32-bit control registers, and four

32-bit system registers.

2.2.1 General Registers (Rn)

The sixteen 32-bit general registers (Rn) are numbered R0âR15. General registers are used for

data processing and address calculation. R0 is also used as an index register. Several instructions

have R0 fixed as their only usable register. R15 is used as the hardware stack pointer (SP). Saving

and recovering the status register (SR) and program counter (PC) in exception processing is

accomplished by referencing the stack using R15.

CPUS200B-000020020700

Rev. 4.00 Dec 05, 2005 page 9 of 564

REJ09B0270-0400

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