SH7046 Datasheet, PDF (466/611 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7046 Series

Section 15 Motor Management Timer (MMT)
15.7 Usage Notes
15.7.1 Module Standby Mode Setting
MMT operation can be disabled or enabled using the module standby control register. The initial
setting is for MMT operation to be halted. Register access is enabled by clearing module standby
mode. For details, refer to section 21, Power-Down Modes.
15.7.2 Notes for MMT Operation
Note that the kinds of operation and contention described below occur during MMT operation.
Contention between Buffer Register Write and Compare Match: If a compare match occurs in
the T2 state of a buffer register (TBRU to TBRW, or TPBR) write cycle, data is transferred from
the buffer register to the compare register (TGR or TPDR) by a buffer operation. The data
transferred is the buffer register write data.
Figure 15.15 shows the timing in this case.
Pφ
Address
Buffer register
write cycle
T1 T2
Buffer register
address
Write signal
Compare match
signal
Interrupt request
signal
Buffer register
Buffer register write data
N
M
Compare register
M
Figure 15.15 Contention between Buffer Register Write and Compare Match
Rev. 4.00 Dec 05, 2005 page 422 of 564
REJ09B0270-0400