SH7046 Datasheet, PDF (17/611 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7046 Series

Item
Page
18.13 Notes on Flash 483 to
Memory Programming 487
and Erasing
Section 19 Mask
490
ROM
21.3.2 Software
501
Standby Mode
Transition to Software
Standby Mode:
22.2 DC
508
Characteristics
Table 22.2 DC
Characteristics
Revision (See Manual for Details)
Newly added
Description amended
The operating mode is selected using mode-setting pins FWP
and MD3 to MD0 as shown in table 3.1. Only the mode 3 is
supported in this LSI. The on-chip ROM is allocated to
addresses H'00000000 to H'0000FFFF of memory area 0
(SH7148), H'00000000 to H'0001FFFF of memory area 0
(SH7048).
Description amended
However, the contents of the CPU's internal registers and on-
chip RAM data are retained as long as the specified voltage is
supplied. …
Table amended
Item
Schmitt trigger
input voltage
IRQ3 to IRQ0,
POE6 to POE0,
TCLKA to TCLKD,
TIOC0A to TIOC0D,
TIOC1A, TIOC1B,
TIOC2A, TIOC2B,
TIOC3A to TIOC3D,
TIOC4A to TIOC4D
Symbol
V_T+ (V_IH)
V_T– (V_IL)
V_T+–V_T–
Min
V_CC – 0.5
–0.3
0.4
Table 22.3 Permitted 510
Output Current Values
Table amended
Item
Output low-level permissible current
(total)
Symbol
Σ
I
OL
Max
110
22.3.9 Port Output 524
Enable (POE) Timing
Table 22.11 Port
Output Enable (POE)
Timing
22.4 A/D Converter 527
Characteristics
Table 22.14 A/D
Converter
Characteristics
Title amended
Table amended
Item
Non-linear error (reference value)
Offset error (reference value)
Full-scale error (reference value)
Rev. 4.00 Dec 05, 2005 page xvii of xliv