SH7046 Datasheet, PDF (417/611 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7046 Series

Section 13 A/D Converter
13.3.2 A/D Control/Status Registers 0 to 2 (ADCSR_0 to ADCSR_2)
ADCSR for each module controls A/D conversion operations.
Bit
7
6
5
4
3
2
1
0
Note:
Initial
Bit Name Value R/W
Description
ADF
0
R/(W)^* A/D End Flag
A status flag that indicates the end of A/D conversion.
[Setting conditions]
• When A/D conversion ends in single mode
• When A/D conversion ends on all specified channels
in scan mode
[Clearing conditions]
• When 0 is written after reading ADF = 1
• When the DTC is activated by an ADI interrupt and
ADDR is read with the DISEL bit in DTMR of DTC = 0
ADIE
0
R/W A/D Interrupt Enable
The A/D conversion end interrupt (ADI) request is
enabled when 1 is set
When changing the operating mode, first clear the ADST
bit in the A/D control registers (ADCRs) to 0.
ADM1
0
R/W A/D Mode 1 and 0
ADM0
0
R/W Select the A/D conversion mode.
00: Single mode
01: 4-channel scan mode
10: Setting prohibited
11: Setting prohibited
When changing the operating mode, first clear the ADST
bit in the A/D control registers (ADCRs) to 0.

1
R
Reserved
This bit is always read as 1, and should only be written
with 1.
CH2
0
R/W Channel Select 2 to 0
CH1
0
R/W Select analog input channels. See table 13.2.
CH0
0
R/W When changing the operating mode, first clear the ADST
bit in the A/D control registers (ADCRs) to 0.
* Only 0 can be written to clear the flag.
Rev. 4.00 Dec 05, 2005 page 373 of 564
REJ09B0270-0400