SH7046 Datasheet, PDF (486/611 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7046 Series

Section 16 Pin Function Controller (PFC)
Initial
Register Bit Bit Name Value R/W Description
PACRL3 2
PA2MD2 0
R/W PA2 Mode
PACRL2 5
PACRL2 4
PA2MD1 0
PA2MD0 0
R/W Select the function of the PA2/IRQ0/PCIO/SCK2
R/W ^pin.
000: PA2 I/O (port)
100: Setting prohibited
001: Setting prohibited 101: PCIO I/O (MMT)
010: Setting prohibited 110: SCK2 I/O (SCI)
011: IRQ0 input (INTC) 111: Setting prohibited
PACRL3 1
PA1MD2 0
R/W PA1 Mode
PACRL2 3
PA1MD1 0
R/W Select the function of the PA1/POE1/TXD2 pin.
PACRL2 2
PA1MD0 0
R/W 000: PA1 I/O (port)
100: Setting prohibited
001: Setting prohibited 101: POE1 input (port)
010: Setting prohibited 110: TXD2 output (SCI)
011: Setting prohibited 111: Setting prohibited
PACRL3 0
PA0MD2 0
R/W PA0 Mode
PACRL2 1
PA0MD1 0
R/W Select the function of the PA0/POE0/RXD2 pin.
PACRL2 0
PA0MD0 0
R/W 000: PA0 I/O (port)
100: Setting prohibited
001: Setting prohibited 101: POE0 input (port)
010: Setting prohibited 110: RXD2 input (SCI)
011: Setting prohibited 111: Setting prohibited
Notes: x: Don’t care
* F-ZTAT only. Setting prohibited for the mask version.
16.1.3 Port B I/O Register (PBIOR)
The port B I/O register (PBIOR) is a 16-bit readable/writable register that is used to set the pins on
port B as inputs or outputs. Bits PB5IOR to PB2IOR correspond to pins PB5 to PB2 (names of
multiplexed pins are here given as port names and pin numbers alone). PBIOR is enabled when
port B pins are functioning as general-purpose inputs/outputs (PB5 to PB2). In other states,
PBIOR is disabled.
A given pin on port B will be an output pin if the corresponding bit in PBIOR is set to 1, and an
input pin if the bit is cleared to 0.
Bits 15 to 6, bit 1, and bit 0 are reserved. These bits are always read as 0 and should only be
written with 0.
The initial vale of PBIOR is H'0000.
Rev. 4.00 Dec 05, 2005 page 442 of 564
REJ09B0270-0400