SH7046 Datasheet, PDF (457/611 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7046 Series

Section 15 Motor Management Timer (MMT)
3. Output Generation Waveform
Output generation waveform U phase A (OGUA) is generated by ANDing CMOUA and
DTGUB, and output generation waveform U phase B (OGUB) is generated by ANDing
CMOUB and DTGUA.
4. PWM Waveform
The PWM waveform is generated by converting the output generation waveform to the output
level set in bits OLSN and OLSP in the timer mode register (TMDR).
Figure 15.5 shows an example of PWM waveform generation (operating mode 3, OLSN = 1,
OLSP = 1).
TPDR
When writing to free
operation address
2Td
Compare output
waveform
Dead time generation
waveform
Output generation
waveform
PWM waveform
Figure 15.5 Example of PWM Waveform Generation
0% to 100% Duty Cycle Output: In the operating modes, PWM waveforms with any duty cycle
from 0% to 100% can be output. The output PWM duty cycle is set using the buffer registers
(TBRU to TBRW).
100% duty cycle output is performed when the buffer register (TBRU to TBRW) value is set to
H'0000. The waveform in this case has positive phase in the 100% on state. 0% duty cycle output
is performed when a value greater than the TPDR value is set as the buffer register (TBRU to
TBRW) value. The waveform in this case has positive phase in the 100% off state.
Rev. 4.00 Dec 05, 2005 page 413 of 564
REJ09B0270-0400