SH7046 Datasheet, PDF (408/611 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7046 Series

Section 12 Serial Communication Interface (SCI)
Initialization
[1]
Start transmission/reception
Read TDRE flag in SSR
[2]
No
TDRE = 1
Yes
Write transmit data to TDR and
clear TDRE flag in SSR to 0
Read ORER flag in SSR
ORER = 1
No
Yes
[3]
Error processing
Read RDRF flag in SSR
[4]
No
RDRF = 1
Yes
Read receive data in RDR, and
clear RDRF flag in SSR to 0
No
All data received?
[5]
Yes
Clear TE and RE bits in SCR to 0
<End>
[1] SCI initialization:
Set the TxD and RxD pins using the PFC.
[2] SCI status check and transmit data write:
Read SSR and check that the TDRE flag
is set to 1, then write transmit data to
TDR and clear the TDRE flag to 0.
Transition of the TDRE flag from 0 to 1
can also be identified by a TXI interrupt.
[3] Receive error processing:
If a receive error occurs, read the ORER
flag in SSR, and after performing the
appropriate error processing, clear the
ORER flag to 0. Transmission/reception
cannot be resumed if the ORER flag is
set to 1.
[4] SCI status check and receive data read:
Read SSR and check that the RDRF flag
is set to 1, then read the receive data in
RDR and clear the RDRF flag to 0.
Transition of the RDRF flag from 0 to 1
can also be identified by an RXI interrupt.
[5] Serial transmission/reception continuation
procedure:
To continue serial transmission/
reception, before the MSB (bit 7) of the
current frame is received, finish reading
the RDRF flag, reading RDR, and
clearing the RDRF flag to 0. Also, before
the MSB (bit 7) of the current frame is
transmitted, read 1 from the TDRE flag to
confirm that writing is possible. Then
write data to TDR and clear the TDRE
flag to 0.
Checking and clearing of the TDRE flag is
automatic when the DTC is activated by a
transmit data empty interrupt (TXI)
request and data is written to TDR. Also,
the RDRF flag is cleared automatically
when the DTC is activated by a receive
data full interrupt (RXI) request and the
RDR value is read.
Note: When switching from transmit or receive operation to simultaneous transmit and receive operations,
first clear the TE bit and RE bit to 0, then set both these bits to 1 simultaneously.
Figure 12.20 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations
Rev. 4.00 Dec 05, 2005 page 364 of 564
REJ09B0270-0400