SH7046 Datasheet, PDF (302/611 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7046 Series

Section 10 Multi-Function Timer Pulse Unit (MTU)
10.7.16 Contention between Overflow/Underflow and Counter Clearing
If overflow/underflow and counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is
not set and TCNT clearing takes precedence.
Figure 10.83 shows the operation timing when a TGR compare match is specified as the clearing
source, and when H'FFFF is set in TGR.
Pφ
TCNT input
clock
TCNT
Counter clear
signal
TGF
H'FFFF
H'0000
TCFV
Disabled
Figure 10.83 Contention between Overflow and Counter Clearing
Rev. 4.00 Dec 05, 2005 page 258 of 564
REJ09B0270-0400