SH7046 Datasheet, PDF (213/611 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7046 Series

Section 10 Multi-Function Timer Pulse Unit (MTU)
Initial
Bit Bit Name value R/W
Description
0
TGFA
0
R/(W) Input Capture/Output Compare Flag A
Status flag that indicates the occurrence of TGRA input
capture or compare match. Only 0 can be written, for flag
clearing.
[Setting conditions]
• When TCNT = TGRA and TGRA is functioning as
output compare register
• When TCNT value is transferred to TGRA by input
capture signal and TGRA is functioning as input
capture register
[Clearing conditions]
• When DTC is activated by TGIA interrupt and the
DISEL bit of DTMR in DTC is 0
• When 0 is written to TGFA after reading TGFA = 1
10.3.6 Timer Counter (TCNT)
The TCNT registers are 16-bit readable/writable counters. The MTU has five TCNT counters, one
for each channel.
The TCNT counters are initialized to H'0000 by a reset.
The TCNT counters cannot be accessed in 8-bit units; they must always be accessed as a 16-bit
unit.
10.3.7 Timer General Register (TGR)
The TGR registers are dual function 16-bit readable/writable registers, functioning as either output
compare or input capture registers. The MTU has 16 TGR registers, four each for channels 0, 3,
and 4 and two each for channels 1 and 2. TGRC and TGRD for channels 0, 3, and 4 can also be
designated for operation as buffer registers. The TGR registers cannot be accessed in 8-bit units;
they must always be accessed as a 16-bit unit. TGR buffer register combinations are
TGRATGRC and TGRBTGRD. The initial value of TGR is H'FFFF.
Rev. 4.00 Dec 05, 2005 page 169 of 564
REJ09B0270-0400