SH7046 Datasheet, PDF (450/611 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7046 Series

Section 15 Motor Management Timer (MMT)
15.3.9 Timer Period Buffer Register (TPBR)
The timer period buffer register (TPBR) is a 16-bit register that functions as a buffer register for
the TPDR register. A value of 1/2 the PWM carrier period should be set as the TPBR value. The
TPBR value is transferred to the TPDR register at the transfer timing set in the TMDR register.
The initial value of TPBR is H'FFFF. Only 16-bit access can be used on TPBR; 8-bit access is not
possible.
15.3.10 Timer Period Data Register (TPDR)
The timer period data register (TPDR) functions as a 16-bit compare register. In the operating
modes, the TPDR register value is constantly compared with the TCNT counter value, and when
they match the TCNT counter changes its count direction from up to down. The initial value of
TPDR is H'FFFF. Only 16-bit access can be used on TPDR; 8-bit access is not possible.
15.4 Operation
When the operating mode is selected, a 3-phase PWM waveform is output with a non-overlap
relationship between the positive and negative phases.
The PUOA, PUOB, PVOA, PVOB, PWOA, and PWOB pins are PWM output pins, the PCIO pin
(when set to output) functions as a toggle output synchronized with the PWM waveform, and the
PCI0 pin (when set to input) functions as the counter clear signal input. The TCNT counter
performs up- and down-count operations, whereas the TDCNT counters perform up-count
operations.
Rev. 4.00 Dec 05, 2005 page 406 of 564
REJ09B0270-0400