SH7046 Datasheet, PDF (148/611 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7046 Series

Section 7 User Break Controller (UBC)
In other CPU data accesses and DTC bus cycles, pulse is output under the conditions similar to
user break interrupt conditions.
Setting the user break interrupt disable (UBID) bit to 1 in UBCR enables trigger output to be
monitored externally without requesting a user break interrupt.
7.5.6 Module Standby Mode Setting
The UBC can set the module disable/enable by using the module standby control register 2
(MSTCR2). By releasing the module standby mode, register access becomes to be enabled.
By setting the MSTP0 bit of MSTCR2 to 1, the UBC is in the module standby mode in which the
clock supply is halted. See section 21, Power-Down Modes, for further details.
Rev. 4.00 Dec 05, 2005 page 104 of 564
REJ09B0270-0400