SH7046 Datasheet, PDF (575/611 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7046 Series

Appendix A Internal I/O Register
Appendix A Internal I/O Register
The column “Access Size” shows the number of bits.
The column “Access States” shows the number of access states, in units of cycles, of the specified
reference clock. B, W, and L in the column represent 8-bit, 16-bit, and 32-bit access, respectively.
A.1 Register Addresses (Order of Address)
Register Name
Abbreviation Bits Address
Module
Access Access
Size
States


 H'FFFF8000 to 


H'FFFF81BF
Serial mode register_2
Bit rate register_2
Serial control register_2
SMR_2
BRR_2
SCR_2
8
H'FFFF81C0 SCI
8, 16 In Pφ cycles
8
H'FFFF81C1 ^{(channel 2)} 8
B: 2
W: 4
8
H'FFFF81C2
8, 16
Transmit data register_2
TDR_2
8
H'FFFF81C3
8
Serial status register_2
SSR_2
8
H'FFFF81C4
8, 16
Receive data register_2
RDR_2
8 H'FFFF81C5
8
Serial direction control register_2 SDCR_2
8
H'FFFF81C6
8


 H'FFFF81C7 to 
H'FFFF81CF
Serial mode register_3
Bit rate register_3
SMR_3
BRR_3
8
H'FFFF81D0 SCI
8, 16
8
H'FFFF81D1 ^{(channel 3)} 8
Serial control register_3
SCR_3
8
H'FFFF81D2
8, 16
Transmit data register_3
TDR_3
8
H'FFFF81D3
8
Serial status register_3
SSR_3
8
H'FFFF81D4
8, 16
Receive data register_3
RDR_3
8 H'FFFF81D5
8
Serial direction control register_3 SDCR_3
8
H'FFFF81D6
8


 H'FFFF81D7 to 
H'FFFF81EF


 H’FFFF81F0 to 


H’FFFF81FF
Rev. 4.00 Dec 05, 2005 page 531 of 564
REJ09B0270-0400