SH7046 Datasheet, PDF (366/611 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7046 Series

Section 12 Serial Communication Interface (SCI)
Initial
Bit Bit Name Value R/W
1
CKS1
0
R/W
0
CKS0
0
R/W
Description
Clock Select 1 and 0
These bits select the clock source for the baud rate
generator.
00: Pφ clock (n = 0)
01: Pφ/8 clock (n = 1)
10: Pφ/32 clock (n = 2)
11: Pφ/128 clock (n = 3)
For the relation between the bit rate register setting and
the baud rate, see section 12.3.9, Bit Rate Register
(BRR). n is the decimal display of the value of n in BRR
(see section 12.3.9, Bit Rate Register (BRR)).
12.3.6 Serial Control Register (SCR)
SCR is a register that performs enabling or disabling of SCI transfer operations and interrupt
requests, and selection of the transfer clock source. For details on interrupt requests, refer to
section 12.7, SCI Interrupts.
Initial
Bit Bit Name Value R/W
7
TIE
0
R/W
6
RIE
0
R/W
5
TE
4
RE
0
R/W
0
R/W
Description
Transmit Interrupt Enable
When this bit is set to 1, TXI interrupt request is enabled.
Receive Interrupt Enable
When this bit is set to 1, RXI and ERI interrupt requests
are enabled.
Transmit Enable
When this bit is set to 1, transmission is enabled.
Receive Enable
When this bit is set to 1, reception is enabled.
Rev. 4.00 Dec 05, 2005 page 322 of 564
REJ09B0270-0400