SH7046 Datasheet, PDF (368/611 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7046 Series

Section 12 Serial Communication Interface (SCI)
12.3.7 Serial Status Register (SSR)
SSR is a register containing status flags of the SCI and multiprocessor bits for transfer. 1 cannot
be written to flags TDRE, RDRF, ORER, PER, and FER; they can only be cleared.
Initial
Bit Bit Name Value R/W
Description
7
TDRE
1
R/(W)^* Transmit Data Register Empty
Displays whether TDR contains transmit data.
[Setting conditions]
• Power-on reset or software standby mode
• When the TE bit in SCR is 0
• When data is transferred from TDR to TSR and data
can be written to TDR
[Clearing conditions]
• When 0 is written to TDRE after reading TDRE = 1
6
RDRF
0
R/(W)^*
• When the DTC is activated by a TXI interrupt request
and transferred data to TDR
Receive Data Register Full
Indicates that the received data is stored in RDR.
[Setting condition]
• When serial reception ends normally and receive data
is transferred from RSR to RDR
[Clearing conditions]
• Power-on reset or software standby mode
• When 0 is written to RDRF after reading RDRF = 1
• When the DTC is activated by an RXI interrupt and
transferred data from RDR
The RDRF flag is not affected and retains their previous
values when the RE bit in SCR is cleared to 0.
Rev. 4.00 Dec 05, 2005 page 324 of 564
REJ09B0270-0400