SH7046 Datasheet, PDF (161/611 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7046 Series

Section 8 Data Transfer Controller (DTC)
Activating
Source
Generator
Activating
Source
DTC Vector
Transfer
Address
DTE Bit Source
Transfer
Destination
CMT (CH0)
CMT (CH1)
CMI0
CMI1
H’00000434
H’00000436
DTED5
DTED4
Arbitrary^*
Arbitrary^*
Arbitrary^*
Arbitrary^*
Reserved

A/D converter
(CH1)
A/D converter
(CH2)
SCI2
SCI3
ADI1
ADI2
RXI_2
TXI_2
RXI_3
TXI_3
H'00000438–
00000443
H'00000444

DTEE5

ADDR

Arbitrary^*
H'00000446 DTEE4 ADDR
Arbitrary^*
H'00000448
H'0000044A
H'0000044C
H'0000044E
DTEE3
DTEE2
DTEE1
DTEE0
RDR_2
Arbitrary^*
RDR_3
Arbitrary^*
Arbitrary^*
TDR_2
Arbitrary^*
TDR_3
Reserved
MMT

TGN
TGM
H'00000450–
H'00000453
H'00000454
H'00000456

DTEF5
DTEF4


Arbitrary^*
Arbitrary^*
Arbitrary^*
Arbitrary^*
Reserved
Software

Write to
DTCSR
H'00000458– 
H'0000049F
H'0400+

DTVEC[7:0]


Arbitrary^* Arbitrary^*
Note: * On-chip memory, on-chip peripheral modules (excluding DTC)
Priority
High
Low
8.3.3 DTC Operation
Register information is stored in an on-chip RAM. When activated, the DTC reads register
information in an on-chip RAM and transfers data. After the data transfer, it writes updated
register information back to the RAM.
Pre-storage of register information in the RAM makes it possible to transfer data over any required
number of channels. The transfer mode can be specified as normal, repeat, and block transfer
mode. Setting the CHNE bit to 1 makes it possible to perform a number of transfers with a single
activation source (chain transfer).
The 32-bit DTSAR designates the DTC transfer source address and the 32-bit DTDAR designates
the transfer destination address. After each transfer, DTSAR and DTDAR are independently
incremented, decremented, or left fixed depending on its register information.
Rev. 4.00 Dec 05, 2005 page 117 of 564
REJ09B0270-0400