SH7046 Datasheet, PDF(16/611 Page) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7046 Series

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SH7046 Datasheet, PDF (16/611 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7046 Series

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Item

18.8.3 Interrupt

Handling when

Programming/Erasing

Flash Memory

Figure 18.10

Erase/Erase-Verify

Flowchart

Page

479

Revision (See Manual for Details)

Figure amended

*1

Erase start

SWE bit â 1

Wait (tSSWE) Âµs

nâ1

Set EBR1 and EBR2

*3

Enable WDT

ESU bit â 1

Wait (tSESU)

E bit â 1

Wait (tSE)

E bit â 0

Wait (tCE)

ESU bit â 0

Wait (tCESU)

Disable WDT

EV bit â 1

Wait (tSEV)

Set block start address as verify address

H'FF dummy write to verify address

Wait (tSEVR)

Read verify data

*2

Increment address

No

No

Verify data = all 1s?

Yes

Last address of block?

Yes

EV bit â 0

Wait (tCEV)

No

*4

All erase block erased?

Yes

SWE bit â 0

Wait (tCSWE)

End of erasing

Rev. 4.00 Dec 05, 2005 page xvi of xliv

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