SH7046 Datasheet, PDF (403/611 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7046 Series

Section 12 Serial Communication Interface (SCI)
interrupt request is generated. Because the TXI interrupt routine writes the next transmit data
to TDR before transmission of the current transmit data has finished, continuous transmission
can be enabled.
3. 8-bit data is sent from the TxD pin synchronized with the output clock when output clock
mode has been specified and synchronized with the input clock when use of an external clock
has been specified.
4. The SCI checks the TDRE flag at the timing for sending the MSB (bit 7).
5. If the TDRE flag is cleared to 0, data is transferred from TDR to TSR, and serial transmission
of the next frame is started.
6. If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, and the TxD pin maintains the
output state of the last bit. If the TEIE bit in SCR is set to 1 at this time, a TEI interrupt
request is generated. The SCK pin is fixed high.
Figure 12.17 shows a sample flowchart for serial data transmission. Even if the TDRE flag is
cleared to 0, transmission will not start while a receive error flag (ORER, FER, or PER) is set to 1.
Make sure to clear the receive error flags to 0 before starting transmission. Note that clearing the
RE bit to 0 does not clear the receive error flags.
Synchroniza-
tion clock
Serial data
Transfer
direction
Bit 0 Bit 1
Bit 0 Bit 4 Bit 5
Bit 6 Bit 7
TDRE
TEND
TXI interrupt
request
generated
Data written to TDR
and TDRE flag cleared
to 0 in TXI interrupt
processing routine
TXI interrupt
request
generated
1 frame
TEI interrupt
request
generated
Figure 12.16 Sample SCI Transmission Operation in Clocked Synchronous Mode
Rev. 4.00 Dec 05, 2005 page 359 of 564
REJ09B0270-0400