SH7046 Datasheet, PDF (128/611 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7046 Series

Section 6 Interrupt Controller (INTC)
Program
execution state
Interrupt?
Yes
NMI?
Yes
No
No
No
User break?
Yes
IRQOUT = low ^*1
Save SR to stack
Save PC to stack
Copy accept-interrupt
level to I3 to I0
IRQOUT = high
*2
Read exception
vector table
Branch to exception
service routine
Level 15
No
interrupt?
Yes
Level 14
No
Yes
I3 to I0 ≤
interrupt?
level 14?
Yes
Level 1
No
No
Yes
I3 to I0 ≤
interrupt?
level 13?
Yes
No
Yes
I3 to I0 =
level 0?
No
Notes: I3 to I0 are Interrupt mask bits of status register (SR) in the CPU
1. IRQOUT is the same signal as interrupt request signal to the CPU (see figure 6.1).
Therefore, IRQOUT is output when the request priority level is higher than the level in bits I3–I0 of SR.
2. When the accepted interrupt is sensed by edge, a high level is output from the IRQOUT pin at the moment when
the CPU starts interrupt exception processing instead of instruction execution (namely, before saving SR to stack).
However, if the interrupt controller accepts an interrupt with a higher priority than the interrupt just to be accepted
and has output an interrupt request to the CPU, the IRQOUT pin holds low level.
Figure 6.3 Interrupt Sequence Flowchart
Rev. 4.00 Dec 05, 2005 page 84 of 564
REJ09B0270-0400