SH7046 Datasheet, PDF (350/611 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7046 Series

Section 11 Watchdog Timer
Initial
Bit Bit Name Value R/W
6
WT/IT
0
R/W
5
TME
0
R/W
4, 3 
All 1 R
Description
Timer Mode Select
Selects whether the WDT is used as a watchdog timer
or interval timer. When TCNT overflows, the WDT either
generates an interval timer interrupt (ITI) or generates a
WDTOVF signal, depending on the mode selected.
0: Interval timer mode
Interval timer interrupt (ITI) request to the CPU when
TCNT overflows
1: Watchdog timer mode
WDTOVF signal output externally when TCNT
overflows^*2.
Timer Enable
Enables or disables the timer.
0: Timer disabled
TCNT is initialized to H'00 and count-up stops
1: Timer enabled
TCNT starts counting. A WDTOVF signal or interrupt
is generated when TCNT overflows.
Reserved
This bit is always read as 1, and should only be written
with 1.
Rev. 4.00 Dec 05, 2005 page 306 of 564
REJ09B0270-0400