SH7046 Datasheet, PDF (525/611 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7046 Series

Section 18 Flash Memory (F-ZTAT Version)
Item
Description
SWE bit protect
When the SWE bit in FLMCR1 is cleared to 0,
all blocks are program/erase-protected. (This
setting should be carried out in on-chip RAM.)
Block protect
By setting the erase block register 1 (EBR1) and
the erase block register 2 (EBR2), erase
protection can be set for individual blocks.
When both EBR1 and EBR2 are set to H’00,
erase protection is set for all blocks.
Emulation protect When the RAMS bit in RAMER is set to 1, all
blocks are program/erase-protected.
Protect Function
Program Erase
Yes
Yes

Yes
Yes
Yes
18.9.3 Error Protection
In error protection, an error is detected when CPU runaway occurs during flash memory
programming/erasing, or operation is not performed in accordance with the program/erase
algorithm, and the program/erase operation is forcibly aborted. Aborting the program/erase
operation prevents damage to the flash memory due to overprogramming or overerasing.
When the following errors are detected during programming/erasing of flash memory, the FLER
bit in FLMCR2 is set to 1, and the error protection state is entered.
• When the flash memory is read during programming/erasing (including vector read and
instruction fetch)
• Immediately after exception handling (excluding a reset) during programming/erasing
• When a SLEEP instruction is executed during programming/erasing
The FLMCR1, FLMCR2, EBR1, and EBR2 settings are retained, however program mode or erase
mode is forcibly aborted at the point when the error is detected. Program mode or erase mode
cannot be re-entered by re-setting the P or E bit. However, PV and EV bit settings are retained,
and a transition can be made to verify mode. The error protection state can be cancelled by the
power-on reset only.
Rev. 4.00 Dec 05, 2005 page 481 of 564
REJ09B0270-0400