SH7046 Datasheet, PDF (523/611 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7046 Series

Section 18 Flash Memory (F-ZTAT Version)
*1
Erase start
SWE bit ← 1
Wait (tSSWE) µs
n←1
Set EBR1 and EBR2
*3
Enable WDT
ESU bit ← 1
Wait (tSESU)
E bit ← 1
Wait (tSE)
E bit ← 0
Wait (tCE)
ESU bit ← 0
Wait (tCESU)
Disable WDT
EV bit ← 1
Wait (tSEV)
Set block start address as verify address
H'FF dummy write to verify address
Wait (tSEVR)
Read verify data
*2
n←n+1
Increment address
No
No
Verify data = all 1s?
Yes
Last address of block?
Yes
EV bit ← 0
Wait (tCEV)
No
*4
All erase block erased?
Yes
SWE bit ← 0
Wait (tCSWE)
EV bit ← 0
Wait (tCEV)
No
n ≥ N?
Yes
SWE bit ← 0
Wait (tCSWE)
End of erasing
Erase failure
Notes: 1. Prewriting (setting erase block data to all 0s) is not necessary.
2. Verify data is read in 32-bit (longword) units.
3. Make only a single-bit specification in the erase block register 1 (EBR1) and the erase block register 2 (EBR2).
4. Erasing is performed in block units. To erase multiple blocks, each block must be erased in turn.
Figure 18.10 Erase/Erase-Verify Flowchart
Rev. 4.00 Dec 05, 2005 page 479 of 564
REJ09B0270-0400