SH7046 Datasheet, PDF (346/611 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7046 Series

Section 10 Multi-Function Timer Pulse Unit (MTU)
POE Timing
Figure 10.117 shows an example of timing from POE input to high impedance of pin.
CK
POE input
CK falling
Falling edge detected
PE9/
TIOC3B
High impedance state
Note: Other large-current pins (PE11/TICO3D, PE12/TIOC4A, PE13/TIOC4B/MRES, PE14/TIOC4C,
PE15/TIOC4D/IRQOUT) also goes to the high impedance state at the same timing
Figure 10.117 Falling Edge Detection Operation
10.9.5 Usage Note
1. To set the POE pin as a level-detective pin, a high level signal must be firstly input to the POE
pin.
2. To clear bits POE0F, POE1F, POE2F, POE3F, and OSF to 0, read registers ICSR1 and OCSR.
Clear bits, which are read as 1, to 0, and write 1 to the other bits in the registers.
Rev. 4.00 Dec 05, 2005 page 302 of 564
REJ09B0270-0400