SH7046 Datasheet, PDF (14/611 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7046 Series

Item
15.3.2 Timer Control
Register (TCNR)
Page
402
15.4.1 Sample
413
Setting Procedure
PWM Output
Generation in
Operating Modes:
4. PWM Waveform
Figure 15.5 Example
of PWM Waveform
Generation
15.7.2 Notes for MMT 424
Operation
Pay Attention to the
Notices Below, When
a Value is Written into
the Timer General
Register U (TGRU),
Timer General
Register V (TGRV),
Timer General
Register W (TGRW),
and in Case of Written
into Free Operation
Address (*):
Writing Operation into 424
Timer Period Data
Register (TPDR) and
Timer Dead Time Data
Register (TDDR)
When MMT is
Operating:
Notes on Halting
425
TCNT Counter
Operation
Revision (See Manual for Details)
Description amended
The timer control register (TCNR) controls the enabling or
disabling of interrupt requests, selects the enabling or disabling
of register access, and selects counter operation or halting .
Figure replaced
Newly added
Newly added
Newly added
Rev. 4.00 Dec 05, 2005 page xiv of xliv