SH7046 Datasheet, PDF (121/611 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7046 Series

Section 6 Interrupt Controller (INTC)
6.4 Interrupt Sources
6.4.1 External Interrupts
There are four types of interrupt sources: NMI, user breaks, IRQ, and on-chip peripheral modules.
Each interrupt has a priority expressed as a priority level (0 to 16, with 0 the lowest and 16 the
highest). Giving an interrupt a priority level of 0 masks it.
NMI Interrupts: The NMI interrupt has priority 16 and is always accepted. Input at the NMI pin
is detected by edge. Use the NMI edge select bit (NMIE) in the interrupt control register 1 (ICR1)
to select either the rising or falling edge. NMI interrupt exception processing sets the interrupt
mask level bits (I3–I0) in the status register (SR) to level 15.
IRQ3 to IRQ0 Interrupts: IRQ interrupts are requested by input from pins IRQ0–IRQ3. Set the
IRQ sense select bits (IRQ0S–IRQ3S) of the interrupt control register 1 (ICR1) and IRQ edge
select bit (IRQ0ES[1:0]–IRQ3ES[1:0]) of the interrupt control register 2 (ICR2) to select low level
detection, falling edge detection, or rising edge detection for each pin. The priority level can be set
from 0 to 15 for each pin using the interrupt priority registers A (IPRA).
When IRQ interrupts are set to low level detection, an interrupt request signal is sent to the INTC
during the period the IRQ pin is low level. Interrupt request signals are not sent to the INTC when
the IRQ pin becomes high level. Interrupt request levels can be confirmed by reading the IRQ
flags (IRQ0F–IRQ3F) of the IRQ status register (ISR).
When IRQ interrupts are set to falling edge detection, interrupt request signals are sent to the
INTC upon detecting a change on the IRQ pin from high to low level. The results of detection for
IRQ interrupt request are maintained until the interrupt request is accepted. It is possible to
confirm that IRQ interrupt requests have been detected by reading the IRQ flags (IRQ0F–IRQ3F)
of the IRQ status register (ISR), and by writing a 0 after reading a 1, IRQ interrupt request
detection results can be withdrawn.
In IRQ interrupt exception processing, the interrupt mask bits (I3–I0) of the status register (SR)
are set to the priority level value of the accepted IRQ interrupt. Figure 6.2 shows the block
diagram of this IRQ3 to IRQ0 interrupts.
Rev. 4.00 Dec 05, 2005 page 77 of 564
REJ09B0270-0400